Collection: Clock Sync Network Adapter 25GbE (with 1PPS) - based on Intel E810-XXVDA2 Product Spec

Host Interface:

  • Compliance with PCIe 4.0
  • Concurrency for 256 non-posted requests

Software Interface:
Base mode VF compatibility with Intel® Adaptive Virtual Functions Specification

  • Tx/Rx Queues
    • 2048 Tx queues and 2048 Rx queues
    • Dynamic allocation of queues to functions and VSIs
  • Interrupts
    • 2048 interrupts vectors, allocated in a flexible manner to queues andother causes
    • Multiple interrupt moderation schemes
    • 20M interrupts/sec
  • Control Queues (a.k.a. Admin Queues)
    • Mailbox Queues for PF-VF and driver-driver
    • Admin Queues for Software-Firmware control flows
    • Sideband Queues for Software to access IPs inside the E810
  • 256 Tx Doorbell (DB) Queues
  • 512 Tx Completion Queues
  • Quanta Descriptor (QD) Queue per Tx queue. Quanta information is also embedded in the Tx doorbell
  • Programmable Rx descriptor fields

Packet Processing:

  • Enhanced Data Plane Development Kit (DPDK)
  • General
    • Stages of parsing, switching, ACLs, classification, packet modification
    • Programmable packet processing pipeline
    • Profile based
    • Programmable actions
    • Propagation of priorities between stages
  • Parser
    • Parses up to 504B from packet header
    • Parse Graph based
    • Session-based parsing
    • Programmable parse engine
  • Binary Classifier (VEB Switch)
    • 768 switch ports (VSIs)
    • Programmable forwarding rules
    • Storm Control
  • ACLs
    • 8K programmable TCAM entries
    • Tiling capability to n*40b width
  • Classification Filters
    • Hash-based statistical distribution
    • Intel® Ethernet Flow Director (Intel® Ethernet FD) flow-based classification
    • Flow-based identification of iWARP and RoCE flows - Programmable rules • Modifier
    • Insert (Tx), remove (Rx), and modify of packet VLANs
    • L3 and L4 checksums and CRC


  • Host virtualization via VMDQ and SR-IOV
  • Up to 256 SR-IOV Virtual Functions
  • Stateless offloads for tunneled packets
  • (network virtualization support)
  • Malicious VF protection
  • Virtual machine load balancing (VMLB)
  • Advanced packet filtering
  • VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags
  • VxLAN, GENEVE, NVGRE, MPLS, VxLAN-GPE with Network Service Headers (NSH) Intel® Ethernet Adaptive Virtual Function drivers


  • iWARP and RoCEv2
  • 256K Queue Pairs (QPs)
  • Send Queue Push Mode

Note: RDMA is not supported when the E810 is configured for >4-port operation.


  • WFQ Transmit scheduler with nine programmable layers
  • Pipeline sharing and starvation avoidance
  • QoS via 802.1p PCP or Differentiated Services Code Point (DSCP) value
  • Packet shaping


  • SMBus operating at up to 1Mb/s
  • DMTF-compliant NC-SI 1.1 Interface at 100Mb/s
  • MCTP over PCIe and SMBus
  • Enterprise-level management schemes via local BMC
  • SNMP and RMON statistic counters
  • Watchdog timer
  • PLDM over MCTP; PLDM Monitoring; PLDM firmware update; PLDM for RDE
  • Firmware Management Protocol support

Power Management:

  • Supports PCI power management states D3hot and D3cold

Time Synchronisation:

  • Time stamp with each Rx packet
  • Selective time stamps for Tx packets
  • IEEE 1588 PTP v1 and v2
  • Time synchronisation signaling with other local platform ingredients


  • Signed UEFI option ROM compatible with HTTPS boot


  • Hardware-based Root of Trust
  • Authentication on NVM Read and Power On
  • Built-in detection of firmware/critical setting corruption with automated device recovery