Intel i226-T1 with SDP headers and a U.FL PPS breakout board
The Intel i226-T1 2.5Gbps exposes 3 software definable pins (SDPs) but Intel has not attached the headers.
So we've done the job for them and made a matching U.FL PPS breakout board to make connections easy.
The i226 is so much cooler than the i210 because it does PTM so you can use PTP_SYS_OFFSET_PRECISE to get near lossless sync between the PHC and the system clock using the igc driver in Linux.
We also provide our breakout board with U.FL to SMA connectors and dip switches for 50ohm termination
Comes with both full and half-height brackets.
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Typically dispatched within 48 hours
Free UK shipping over £500, worldwide delivery
3 month manufacturer warranty on all hardware
Direct support from timing engineers
| 5+ units | 5% off |
| 10+ units | 10% off |
| 25+ units | 15% off |
Shipping and delivery
Shipping and delivery
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International customs charges and import duties are the responsibility of the buyer and are not collected by Timebeat.
Warranty
Warranty
All hardware carries a 3 month manufacturer warranty covering manufacturing defects. Damage caused in use or installation is not covered.
If an item arrives damaged, faulty or not as ordered, contact sales@timebeat.app and we will repair, replace or refund it. Your statutory rights are not affected.
Technical support
Technical support
Speak directly to the engineers who design and build these products. Documentation, setup guides and the support portal live at support.timebeat.app, and technical questions reach a real engineer at sales@timebeat.app.
The Intel i226-T1 2.5Gbps exposes 3 software definable pins (SDPs) but Intel has not attached the headers.
So we've done the job for them and made a matching U.FL PPS breakout board to make connections easy.
The i226 is so much cooler than the i210 because it does PTM so you can use PTP_SYS_OFFSET_PRECISE to get near lossless sync between the PHC and the system clock using the igc driver in Linux.
We also provide our breakout board with U.FL to SMA connectors and dip switches for 50ohm termination
Comes with both full and half-height brackets.
EXTERNAL INTERFACES
PCI Express 3.1:
5GT/s Support for x1 width (Lane).
Network Interfaces:
Integrated MAC + BASE-T PHY.
MDI (Copper) standard IEEE 802.3 Ethernet interface for 2500BASE-T, 1000BASE-T, 100BASE-TX, and 10BASE-TE applications (802.3, 802.3u, 802.3bz, and 802.3ab).
ETHERNET FEATURES
IEEE 802.3 auto-negotiator:
Automatic link configuration for speed duplex and flow control
IEEE 802.3x and IEEE 802.3z compliant flow control support with software-controllable Rx thresholds and Tx pause frames:
Local control of network congestion levels.
Automatic cross-over detection function (MDI/ MDI-X):
Frame loss reduced from receive overruns.
IEEE 1588 protocol and 802.1AS implementation:
Time-stamping and synchronization of time sensitive applications.
Distribute common time to media devices.
Supporting Time Sensitive Networking (TSN) Capabilities:
IEEE 802.1Qbu, 802.3br, 802.1Qbv, 802.1AS-REV, 802.1p,Q, and 802.1Qav.
Supports Time-based transmission.
Any Tx and Rx queues can be used for scheduled traffic or best effort traffic.
Supports Forwarding and Queuing Enhancements for Time-Sensitive Streams.
STATELESS OFFLOADS AND PERFORMANCE FEATURES
TCP/UDP, IPv4 checksum offloads (Rx/ Tx):
Offloading capabilities and improved CPU usage.
Extended Tx descriptors.
Checksum and segmentation capability extended to new standard packet type.
Transmit Segmentation Offloading (TSO) (IPv4, IPv6):
Increased throughput and lower processor usage.
Interrupt throttling control:
Limits maximum interrupt rate and improves CPU usage.
Low-Latency Interrupts:
Based on the sensitivity of the incoming data, the controller can bypass the automatic moderation of time intervals between the interrupts.
Legacy and Message Signal Interrupt (MSI):
Interrupt mapping.
Message Signal Interrupt Extension (MSI-X):
Dynamic allocation of up to 5 vectors per port.
Scalable I/O for Linux environments (IPv4, IPv6, TCP/UDP):
Improves the system performance related to handling of network data on multiprocessor systems.
Support for packets up to 9.5 KB (Jumbo Frames):
Enables faster and more accurate throughput of data.
PCIe v3.1 support:
Includes additions to PCIe to support low power link states.
Descriptor ring management hardware for Transmit and Receive:
Optimized descriptor fetch and write-back for efficient system memory and PCIe bandwidth usage.
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